Increasing interconnection density is one of many pressures in the electronic industry. As all components shrink in size, interconnection designs must keep pace. There is a need for very dense, high speed (30 Gb/s+) routing configurations. In addition, it is desirable to keep manufacturing costs low by continuing to use standard low cost printed circuit board (PCB) design rules. Recent and future communication standard interfaces consist of an increasing number of parallel channels while dramatically increasing the line rate per channel and decreasing the available PCB real estate at the same time. This represents a major challenge in system signal integrity. Embodiments of the present disclosure provide high channel density at a low manufacturing cost, while maintaining acceptable signal performance.